Business Administration | |||||
Bachelor | Length of the Programme: 4 | Number of Credits: 240 | TR-NQF-HE: Level 6 | QF-EHEA: First Cycle | EQF: Level 6 |
School/Faculty/Institute | Faculty of Engineering | |||||
Course Code | EE 471 | |||||
Course Title in English | Introduction to Embedded Systems | |||||
Course Title in Turkish | Gömülü Sistemlere Giriş | |||||
Language of Instruction | EN | |||||
Type of Course | Flipped Classroom,Laboratory Work | |||||
Level of Course | Introductory | |||||
Semester | Fall | |||||
Contact Hours per Week |
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Estimated Student Workload | 155 hours per semester | |||||
Number of Credits | 6 ECTS | |||||
Grading Mode | Standard Letter Grade | |||||
Pre-requisites |
EE 203 - Digital Systems Design |
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Co-requisites | None | |||||
Expected Prior Knowledge | Prior knowledge digital systems, gate level design of combinational and sequential circuits, circuit analysis is expected. | |||||
Registration Restrictions | Only Undergraduate Students | |||||
Overall Educational Objective | To learn the basics of embedded systems classification, composition of state machines, system design methodologies, embedded system components such as embedded microprocessor, microcontrollers, FPGAs, sensors, actuators and memory architectures. | |||||
Course Description | This course provides an introduction to embedded systems design. The following topics are covered: overview of embedded systems, state machine design and algorithmic state machines (ASM), hardware design and implementation for embedded systems, some hardware components of embedded systems: FPGAs, microcontrollers, microprocessors, sensors, actuators, memory architectures, FPGA programming with Verilog HDL, interfacing FPGA with microprocessor. Students will complete a microprocessor and FPGA based embedded system design project. |
Course Learning Outcomes and CompetencesUpon successful completion of the course, the learner is expected to be able to:1) understand the structure and basic elements of an embedded system; 2) compose embedded system models and FPGA modules using Verilog HDL; 3) construct a custom system such as a soft-processor on FPGA through embedding; 4) design an FPGA+soft-processor based embedded system; 5) compile a system by designing individual components as a part of team; 6) report and present a designed embedded system to a wide audience. |
Program Learning Outcomes/Course Learning Outcomes | 1 | 2 | 3 | 4 | 5 | 6 |
---|---|---|---|---|---|---|
1) Has a broad foundation and intellectual awareness with exposure to mathematics, history, economics, and social sciences | ||||||
2) Demonstrates knowledge and skills in different functional areas of business (accounting, finance, operations, marketing, strategy, and organization) and an understanding of their interactions within various industry sectors | ||||||
3) Applies theoretical knowledge as well as creative, analytical, and critical thinking to manage complex technical or professional activities or projects | ||||||
4) Exhibits an understanding of global, environmental, economic, legal, and regulatory contexts for business sustainability | ||||||
5) Demonstrates individual and professional ethical behavior and social responsibility | ||||||
6) Demonstrates responsiveness to ethnic, cultural, and gender diversity values and issues | ||||||
7) Uses written and spoken English effectively (at least CEFR B2 level) to communicate information, ideas, problems, and solutions | ||||||
8) Demonstrates skills in data and information acquisition, analysis, interpretation, and reporting | ||||||
9) Displays computer proficiency to support problem solving and decision-making | ||||||
10) Demonstrates teamwork, leadership, and entrepreneurial skills | ||||||
11) Displays learning skills necessary for further study with a high degree of autonomy |
N None | S Supportive | H Highly Related |
Program Outcomes and Competences | Level | Assessed by | |
1) | Has a broad foundation and intellectual awareness with exposure to mathematics, history, economics, and social sciences | N | |
2) | Demonstrates knowledge and skills in different functional areas of business (accounting, finance, operations, marketing, strategy, and organization) and an understanding of their interactions within various industry sectors | N | |
3) | Applies theoretical knowledge as well as creative, analytical, and critical thinking to manage complex technical or professional activities or projects | N | |
4) | Exhibits an understanding of global, environmental, economic, legal, and regulatory contexts for business sustainability | N | |
5) | Demonstrates individual and professional ethical behavior and social responsibility | N | |
6) | Demonstrates responsiveness to ethnic, cultural, and gender diversity values and issues | N | |
7) | Uses written and spoken English effectively (at least CEFR B2 level) to communicate information, ideas, problems, and solutions | S | Presentation |
8) | Demonstrates skills in data and information acquisition, analysis, interpretation, and reporting | S | Participation |
9) | Displays computer proficiency to support problem solving and decision-making | N | |
10) | Demonstrates teamwork, leadership, and entrepreneurial skills | S | Participation |
11) | Displays learning skills necessary for further study with a high degree of autonomy | S | Participation |
Prepared by and Date | TUBA AYHAN , June 2019 |
Course Coordinator | TUBA AYHAN |
Semester | Fall |
Name of Instructor | Asst. Prof. Dr. TUBA AYHAN |
Week | Subject |
1) | Overview of embedded systems |
2) | FPGA based embedded systems and Verilog HDL |
3) | FPGA programming with Verilog HDL |
4) | State machine design and algorithmic state machines (ASM) |
5) | Peripherals: sensor, actuators and GPIO operations |
6) | Memory structures |
7) | Programmable interface |
8) | Serial interface protocols I2C, SPI, UART |
9) | Hardcore/softcore processors: ARM and NIOS II |
10) | Embedding NIOS II on FPGA |
11) | Internal bus for FPGA |
12) | Project part 1: software design on NIOS II |
13) | Project part 2: hardware design on FPGA with embedded NIOS II |
14) | Project part 3: Demo and presentation |
15) | Final Exam/Project/Presentation Period |
16) | Final Exam/Project/Presentation Period |
Required/Recommended Readings | 1. Lee and Seshia, Introduction to Embedded Systems, Second Edition, MIT Press, 2017 (online available at http://leeseshia.org/index.html) (part I and II) 2. Altera, Quartus II Handbook, 2017 (online available at https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii5v1.pdf) Altera, Embedded Design Handbook, 2017 (online available at https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed_handbook.pdf) | |||||||||||||||
Teaching Methods | Contact hours using “Flipped Classroom” as an active learning technique. | |||||||||||||||
Homework and Projects | Students will complete a microprocessor and FPGA based embedded system design project. | |||||||||||||||
Laboratory Work | Students will carry out (7 experiments) on FPGA programing and embedding NIOS II. | |||||||||||||||
Computer Use | Student is to use Quartus, Qsys and Modelsim tools for their designs. | |||||||||||||||
Other Activities | None | |||||||||||||||
Assessment Methods |
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Course Administration |
Instructor’s office and phone number: 5th Floor office hours: email address: ayhant@mef.edu.tr Policies: • Missing a midterm: Provided that proper documents of excuse are presented, a make-up exam will be given for the missed midterm. • Missing project: Fail. • Lab reports are due 1 week after it is completed. Late reports will be downgraded by 20% for each day passed the due date. • Exams are in closed-notes and closed-books format. • To be eligible of submitting the project, you should attend 3 out of 4 lab sections and your weighted average before the project submission should be at least 25 (out of 100). • A reminder of proper classroom behavior, code of student conduct: YÖK Regulations Academic Dishonesty and Plagiarism: YÖK Regulations |
Activity | No/Weeks | Hours | Calculation | ||||
No/Weeks per Semester | Preparing for the Activity | Spent in the Activity Itself | Completing the Activity Requirements | ||||
Course Hours | 14 | 2 | 3 | 70 | |||
Laboratory | 7 | 1 | 3 | 3 | 49 | ||
Project | 1 | 20 | 2 | 22 | |||
Midterm(s) | 2 | 5 | 2 | 14 | |||
Total Workload | 155 | ||||||
Total Workload/25 | 6.2 | ||||||
ECTS | 6 |